3D-COSTAR: A Cost Model for 3D Stacked ICs
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چکیده
Selecting appropriate and efficient test flow for a 3D Stacked IC (3D-SIC) is crucial for overall cost optimization. This paper presents 3D-COSTAR, a tool that considers costs involved in the whole 3D-SIC chain, including design, manufacturing, test, packaging and logistics (e.g. related to shipping wafers between a foundry and a test house); and provides the estimated overall cost and cost breakdown for a given input parameter set (e.g., test flows, die yield and stack yield). As a case study, the tool is used to compare the overall cost of producing a 3D-SIC by an Integrated Device Manufactures (IDM) and a fab-less company. For the fab-less company, we assume that each step in the 3D-SIC chain is outsourced to a different company. Therefore, additional logistics costs and high quality test contracts are in place; while an IDM does not have these constraints. Simulation results show that by choosing an appropriate test flow the overall 3D-SIC cost for the IDM can be reduced up to 20% for a 5-layered 3D-SIC.
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